RN-HDL FPGA / CPLD Training System

Experiments

• Implementation the basic logical gates with 2 and 3 inputs
• Implementation the comparative and arithmetic operators
• Implementation the half adder and full adder
• Implementation the decoder and encoder
• Implementation the multiplexer and demultiplexer
• Implementation the bit parity generator
• Implementation the basic flip-flops with preset and clear inputs
• Implementation the up, down, ring and Johnson counter
• Implementation the different shift registers
• Setting up the 7-segment and HEX display
• Setting up the dot-matrix display
• Setting up the 4×4 keypad
• Remove the bounces of push button switches using MC14490
• Setting up the stepper motor
• Setting up the DC motor
• Setting up the ADC circuit based on ADC0809
• Setting up the DAC circuit based on DAC0800
• Interface to computer using RS-232 converter and serial port
• Wireless transmission of coded data using HM-T and HM-R transmitter/receiver
• Wireless transmission of coded data using infrared transmitter and receiver
• Decode the tone signals using MT8870